The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices requires design features of 0.25 microns and under, such as 0.18 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor manufacturing techniques.
In order to reduce the number of manufacturing steps, such as masking, thereby increasing manufacturing throughput, the N-channel and P-channel transistors of a CMOS semiconductor device are conventionally exposed to similar processing conditions, such as spacer formation on the sidewalls of gate electrodes and heat treatment. Typically, the entire semiconductor wafer is placed in a furnace and subjected to heat treatment when activation annealing for converting impurity implants into source/drain regions. The economic advantage attendant upon increased manufacturing throughput comes at a price, however, in that the performance characteristics of the N-channel transistor and P-channel transistor cannot be individually tailored or optimized. For example, the diffusion coefficients of P-type impurity atoms, such as boron, are typically greater than those of N-type impurity atoms. During activation annealing of the N-channel transistor source/drain regions, the P-channel lightly doped implants are subjected to elevated temperatures and, hence, undergo diffusion. Accordingly, it is difficult to form the P-channel transistor with a shallow lightly doped junction depth (X.sub.J).
As design features shrink to less than about 0.25 microns, the disadvantages attendant upon uniform processing of N-channel and P-channel transistors of a CMOS semiconductor device are exacerbated. For example, for design features of about 0.25 microns, it is necessary to significantly reduce the X.sub.J to less than about 800 .ANG.. This, in itself, is difficult to achieve, let alone in a P-channel transistor of a CMOS device employing conventional methodology comprising activation annealing to activate both the N-channel transistor and P-channel transistor implants to form source/drain regions. In addition, it is generally desirable to form the P-channel transistor with a channel region having a channel length greater than that of the channel region of the N-channel transistor, particularly in semiconductor devices having sub-micron features, to avoid the short channel effect characteristic of P-type transistors.
Conventional methodology for manufacturing a CMOS device comprises separately ion implanting to form N-channel and P-channel lightly doped implants using the N-channel transistor gate electrode and P-channel transistor gate electrode as masks, respectively. Subsequently, dielectric sidewall spacers are formed on the side surfaces of both gate electrodes. The P-channel transistor is then typically masked and N-type impurities are ion implanted into the semiconductor substitute using the gate electrode and sidewall spacers thereon as a mask to form moderately or heavily doped implants. High temperature activation annealing is then conducted to activate the N-channel source/drain regions, typically at about 1050.degree. C. for about 30 seconds, i.e., rapid thermal annealing (RTA). During activation annealing, the implanted N-type impurities diffuse into the proper lattice sites and implantation damage is reduced, thereby reducing junction leakage. The N-type impurity implants are generally activated at higher temperatures than those employed to activate the P-channel implants, since the N-channel implants are typically more difficult to activate than the P-channel source/drain implants. However, at the time of high temperature activation annealing to form the N-channel source/drain regions, the lightly doped P-channel implants diffuse to a great extent as P-type impurities typically diffuse significantly faster than N-type impurities. Subsequently, the N-channel transistor region is masked and P-type impurities are ion implanted to form moderately or heavily doped implants. Activation annealing is then conducted, at a temperature of about 1000.degree. C., to activate the P-channel source/drain regions.
In practicing such conventional methodology, the lightly doped P-channel implants are exposed to both the N-channel activation annealing and the P-channel activation annealing, thereby undesirably increasing the X.sub.J beyond the targeted maximum of about 800 .ANG.. Accordingly, there exists a need for semiconductor methodology enabling independent optimization of performance for N-channel and P-channel transistors of a CMOS device, particularly in forming P-channel transistors having a shallow X.sub.j.